Multithreshold Cmos Sleep Stack and Logic Stack Technique for Digital Circuit Design
نویسندگان
چکیده
Power optimization is the major problem in digital circuit design. In this paper using MTCMOS and stack techniques are proposed. Multi threshold CMOS sleep stack and logic stack, super cutoff sleep stack and logic stack are proposed. Stacking is introduced in MTCMOS concept which decreases leakage power based on the power dissipation of pMOS and nMO Stransistor. MTCMOS technique uses multiple voltages in the circuit which is the main advantage of this. Power dissipation, propagation delay and power delay product are calculated. Constrains like power, delay is compared with the existing techniques. It is proved that proposed technique is better than previous technique. Simulation results are given using HSpice.
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